This application claims priority from Korean Patent Application No. 2003-20478, filed on Apr. 1, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor field effect transistor (hereinafter, referred to as “MOSFET”) device and a method of manufacturing the same. More particularly, the present invention relates to a silicon-on-insulator (SOI) MOSFET device with a nanoscale channel and a method of manufacturing the same.
2. Description of the Related Art
As silicon semiconductor device technologies progress, the size of a semiconductor device is scaled down to accomplish low power consumption, high integration, and high-speed driving. In particular, metal-oxide-semiconductor (MOS) device technology, which occupies most of silicon semiconductor device technologies, must satisfy the requirement of a decrease in a channel length, a source and drain junction depth, and a gate dielectric film thickness. In addition, devices of the same size can have improved characteristics by an increase in a driving current and a decrease in a leakage current.
A conventional fabrication process for a transistor with a nanoscale channel requires very strict process conditions and high-priced process equipment. That is, since a nanoscale conductive channel cannot be formed by a conventional photolithography process, new patterning technologies such as direct e-beam writing, extreme ultraviolet (EUV) exposure, and X-ray exposure must be used. Therefore, a manufacture cost of a silicon device increases and mass production is difficult. In addition, with respect to conventional ion implantation or plasma doping technologies used in forming a source and a drain, it is difficult to form an ultra-shallow junction, and ion implantation causes a substrate defect, thereby lowering device properties. Also, high-priced junction formation equipment is required. In addition, as the sizes of devices decrease, the thickness of a gate dielectric film decreases, thereby increasing a gate leakage current. In order to solve these problems, studies on a gate dielectric film made of a highly dielectric material have been done. However, since formation of a gate dielectric film precedes formation of a source and a drain in conventional transistor device fabrication technology, the application of a subsequent thermal activation process is restricted. Also, when a nanoscale device is manufactured using a monocrystalline silicon substrate instead of an SOI substrate, there arise serious problems in that it is difficult to form shallow junction for a source and a drain and to obtain device reliability and insulation between devices. In addition, as the doping concentration of an impurity diffusion layer increases, a junction capacity increases.
In this regard, U.S. Pat. No. 6,033,963 discloses a method of forming a metal gate for a CMOS device using a replacement gate process. However, the replacement gate process is very complicated, and it is difficult to perform self-alignment of a gate and a source/drain.
U.S. Pat. No. 6,225,173 B1 discloses a method of manufacturing a MOSFET device with an ultra-shallow source/drain junction using a damascene process. In this patent, however, a complicated process, such as using a CMP process for removal of an insulator, and a high process cost are required.
Therefore, in order to solve the above-described problems and to realize a high performance and highly integrated circuit, a novel method of manufacturing a nanoscale device is necessary.